1. Field of the Invention
The present invention generally relates to an apparatus and method for using a silicon containing photoresist material in integrated circuit fabrication, and more particularly, to the use of a silicon containing photoresist material for use in etching amorphous carbon films in integrated circuit fabrication processes.
2. Description of the Related Art
In recent years integrated circuits have evolved into complex devices that commonly include millions of transistors, capacitors, resistors, and other electronic components on a single chip. Therefore, there is an inherent demand for increased circuit densities, as well as a continual demand for faster and more efficient circuit components. The combined demands for faster circuits having greater circuit densities imposes corresponding demands on the materials used to fabricate such integrated circuits. In particular, as the dimensions of integrated circuit components are reduced to sub-micron-sized dimensions, it has been necessary to investigate the use of low resistivity conductive materials, such as copper and/or low dielectric constant insulating materials having a dielectric constant less than about 4.5, in order to improve the electrical performance of these faster and more dense circuit components.
The demands for faster components having greater circuit densities also imposes demands on process sequences used for integrated circuit manufacture. For example, in process sequences using conventional lithographic techniques, a layer of energy sensitive resist is generally formed over a stack of material layers on a substrate. An image of a pattern may then be introduced into the energy sensitive resist layer. Thereafter, the pattern introduced into the energy sensitive resist layer may be transferred into one or more layers of the material stack formed on the substrate using the layer of energy sensitive resist as a mask. The pattern introduced into the energy sensitive resist may then be transferred into a material layer(s) using a chemical and/or physical etchant. A chemical etchant is generally designed to have a greater etch selectivity for the material layer(s) than for the energy sensitive resist, which generally indicates that the chemical etchant will etch the material layer(s) at a faster rate than it etches the energy sensitive resist. The faster etch rate for the one or more material layers of the stack typically prevents the energy sensitive resist material from being consumed prior to completion of the pattern transfer.
However, demands for greater circuit densities on integrated circuits have necessitated smaller pattern dimensions i.e., sub-micron dimensions. As these pattern dimensions are reduced to accommodate sub-micron type devices, the thickness of the energy sensitive resist is generally reduced correspondingly in order to proportionally control pattern resolution. These substantially thinner resist layers, such as, layers having a thickness of less than about 6000 Å, for example, may, however, be insufficient to mask underlying material layers during a pattern transfer step using chemical etchants.
Therefore, if the thinner resist layer is insufficient to mask the underlying material layers, then an additional intermediate oxide layer i.e., silicon dioxide, silicon nitride, or other similar oxide material, which is often termed a hardmask, may be used between the energy sensitive resist layer and the underlying material layers in order to facilitate pattern transfer into the underlying material layers. However, some material structures, such as damascene, for example, include silicon dioxide and/or silicon nitride layers therein, and therefore, these structures generally cannot be patterned using a silicon dioxide or silicon nitride hardmask, as the same material is used in the structure itself. Nevertheless, although the implementation of the intermediate layer is generally effective in masking the underlying layers, the process of forming the intermediate layer and removing the intermediate layer adds additional overhead and process time to the throughput rate of devices implementing this layer.
Resist patterning problems are further compounded when lithographic imaging tools having deep ultraviolet (DUV) imaging wavelengths, i.e., wavelengths less than about 250 nanometers, are used to generate the resist patterns. The DUV imaging wavelengths are generally known to improve resist pattern resolution as a result of the diffraction effects being reduced at the shorter wavelengths. However, the increased reflective nature of many underlying materials, i.e., polysilicon and metal silicides, for example, may operate to degrade the resulting resist patterns at DUV wavelengths.
One technique proposed to minimize reflections from an underlying material layer uses an anti-reflective coating (ARC). The ARC is formed over the reflective material layer prior to resist patterning. The ARC generally suppresses the reflections off the underlying material layer during resist imaging, thereby providing more accurate pattern replication in the layer of energy sensitive resist.
A number of ARC materials have been suggested for use in combination with energy sensitive resists. For example, U.S. Pat. No. 5,626,967 issued May 6, 1997 to Pramanick describes the use of titanium nitride anti-reflective coatings. However, titanium nitride is exhibits increasingly metallic characteristics as the exposure wavelength is reduced below 248 nm, as titanium nitride is known to exhibit high reflectivity for DUV radiation, and therefore, is generally known not to be an effective anti-reflective coating for DUV wavelengths.
U.S. Pat. No. 5,710,067 issued Jan. 20, 1998 to Foote discloses the use of silicon oxynitride antireflective films. Silicon oxynitride films are difficult to remove and typically leave residues behind that potentially interfere with subsequent integrated circuit fabrication steps.
In view of conventional photolithographic techniques, there exists a need in the art for a photoresist layer useful for integrated circuit fabrication, wherein the photoresist layer may be used without an intermediate layer, and further, without an ARC layer. There exists a further need for a photoresist capable of forming a silicon oxide hard mask on the surface of the photoresist, wherein the silicon oxide hard mask is configured to provide additional selectivity between the photoresist and an underlying material layer, which may be amorphous carbon, for example.